As technology advances, the number of transistors within a die, the number of die fabricated on a semiconductor wafer, and the overall size of the semiconductor wafer all increase. Consequently, variations in the manufacturing process may result in transistors across a semiconductor wafer having varying operational performance characteristics. This may result in die within close proximity of each other on a semiconductor wafer to operate differently even though they were manufactured using substantially the same process.
In addition, the physical arrangement of transistors within a die as compared to the arrangement of other transistors may result in some of the transistors undergoing greater electro-mechanical stress during operation. This problem may be further acerbated by the operating conditions, such as temperature, for example, which may be imposed upon the device by a consumer. If the variation in performance becomes too extreme, the device may operate outside the range deemed acceptable by a customer. If this occurs, the device may not be sold and is usually scrapped for failing to meet operational conditions. Therefore, the overall cost of manufacturing semiconductor die is increased due at least in part to the loss of die that had to be scrapped due to their unacceptable performance.
This problem of performance variation may be addressed by adding additional circuitry to a die that modulates the performance of some of the transistors within the die. One such technique is described in U.S. Pat. No. 5,869,983 entitled "Method and Apparatus for Controlling Compensated Buffers", issued to IIkabahar et al., on Feb. 9, 1999, which is assigned to the same assignee as the present invention. However, it may be desirable to provide a solution that has even greater flexibility.